1. Field of Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having an output circuit that is provided with an electrostatic protection countermeasure.
2. Description of Related Art
Internal circuits of a semiconductor device may be destroyed if a high voltage due to static electricity is applied to input terminals or output terminals. This type of electrostatic destruction becomes problematic particularly in CMOS type semiconductor devices. A related art semiconductor device is described with reference to FIGS. 6 and 7.
FIG. 6 is a plan view of a related art semiconductor device. FIG. 7 is a cross-sectional view of the related semiconductor device taken along plane B-B′ shown in FIG. 6. In FIGS. 6 and 7, an interlayer dielectric film and a wiring layer are omitted. A gate electrode 24 is formed over a P− type semiconductor substrate 20 through a gate dielectric film 23, and sidewalls 25 are formed on side walls of the gate electrode 24. An N+ type drain region 26 and an N+ type source region 27 are formed in the semiconductor substrate 20 on both sides of the gate electrode 24. A salicide layer 28 is formed on the N+ type drain region 26, and the salicide layer 28 is connected to an output terminal through a wiring electrode 32 and a wiring connected thereto. A salicide layer 29 is formed on the N+ type drain region 27, and the salicide layer 29 is connected to a wiring to supply a power supply potential VSS on a low potential side through a wiring electrode 31 or 33.
The semiconductor device is designed to protect elements that are connected to the output terminal. More specifically, the wiring electrode 32 is spaced a great distance from the gate electrode 24, such that heat generated at a hot spot (heat generating spot) that occurs adjacent to the gate electrode does not propagate to the wiring electrode 32. Also, salicide layer prohibition regions 30 are provided adjacent to the gate electrode 24.
However, with further miniaturization of semiconductor devices in recent years, impurity diffusion layers tend to be formed shallower. As a result, there is a problem in that current concentration is apt to occur at the drain or the collector, and the electrostatic breakdown voltage of a semiconductor device lowers.
Japanese Laid-open patent application (Tokkai) HEI 9-306998 describes a MOS transistor structure having an electrostatic breakdown preventing circuit. In the MOS transistor structure, the diffusion resistance of the drain region is increased by many isolated islands that are uniformly distributed across the entire drain diffusion layer. However, by simply increasing the diffusion resistance of the drain region, although the MOS transistor may become more resistive against electrostatic breakdown, it fails to achieve its original capacity.